Advanced Micro Devices, Inc. (AMD), Santa Clara, Calfornia
Member of Technical Staff (MTS) (Jul 2022 - Present)
AMD Research and Advanced Development- Exploring and developing techniques to improve compute bandwidth and energy savings for next-gen AMD EPYC processors.
Georgia Institute of Technology, Atlanta, Georgia
Graduate Research Assistant, School of Electrical and Computer Engineering (Aug 2016 - May 2022)
Advisor: Prof. Milos Prvulovic, Professor, School of Computer Science & Prof. Alenka Zajic, Professor, School of Electrical and Computer Engineering - Developed a new technique for profiling and monitoring IoT and embedded devices without interfering with the native execution, in a completely contact-less manner, by leveraging their electromagnetic (EM) side-channel.
- Created a zero-overhead memory subsystem profiler (EMProf) that identifies and profiles microarchitectural events such as last-level cache misses by analyzing the varying power levels in the EM emanations.
- Designed a novel system profiler (PRIMER) for profiling interrupts on resource-constrained devices.
- Developed network application fingerprinting based on system events corresponding to various network activities.
Graduate Teaching Assistant, ECE 2031: Digital Design Lab (Aug 2015 - Jul 2016)
Instructors: Dr. Tom Collins & Kevin Johnson, School of ECE - Conducting labs for ~70 students working on hardware design and prototyping on Altera DE2 FPGA.
- Grade reports, presentations, technical documents and proposals pertaining to IEEE guidelines, and hold individual consultations as a part of the Undergraduate Professional Communication Program.
Intel Corporation, Folsom, California
Graphics Hardware Engineer Intern (May 2018 - Aug 2018)
KC Validation and Execution - Developed tests to validate display functional blocks for Intel Graphics Icelake series processors for Apple MacBook Pro.
- Created automated scripts to extract color pipeline register data of HDR/SDR pipes, and display device parameters.
Summer Trainee (June 2014 - July 2014)
Mentor: Mr. Sunny Rajput, R&D-Electronic Systems - Programmed Altera FPGA to perform Byte Write operation on the Serial EEPROM T24C02B using I2C protocol and subsequently Random Read on the same location.
- Created a PC interface to control the output of DAC IC AD5382, which was programmed by the FPGA depending upon the desired output voltage taken from the user via keyboard using the RS232 protocol.
Research Intern (Jun 2013 - Jul 2013)
Mentor: Mr. Asim Kar, Scientific Officer, Department of Remote Handling and Robotics - Worked on “Obstacle Avoidance: A Potential Field Theory Approach” project.
- Studied and implemented various popular sensor-based reactive navigation methods. Experimented with the potential field approach and observed results in various simulated environments.
- Designed a novel sector-based navigation algorithm to overcome the shortcomings of the conventional approach. This algorithm analyzes the sensor data projecting into sector map and drives the robot through free sectors closer to the goal.
- The simulation results show that the developed method provides much smoother trajectories for the robot even in cluttered situations.
- Compared this navigation algorithm with the conventional Potential Field Theory algorithm in both a simulated environment based on Microsoft Visual Studio, and on a real robot equipped with laser sensor.
